A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of metal wiring called traces. In VLSI chips, these metal patterns are multilayered and separated by layers of an insulating material. Interlevel contacts between metal wiring patterns are made by through-holes (aka via holes), which are etched through the layers of insulating material. Typical chip designs consist of one or two wiring levels, with three wiring levels being the current state of the art. Circuit cost and performance continue to place demand on the fabrication processes, so that adding supplementary wiring levels can be competitive even though additional processing steps are required. However, the technique using via holes, although widely used today, has multiple limitations and drawbacks in that, as the number of metallization layers increases, wiring and level-to-level alignment become increasingly difficult.
In the art of making VLSI semiconductor devices, a silicon wafer is metallized with circuitry traces and pads, typically of aluminum-copper alloy, sputter coated overall with SiO2, resulting in an irregular topography. It is necessary to achieve a smooth topography without damaging the circuitry traces and pads or insulation in order to align devices precisely level-to-level.
Etch stops and polishing slurries are known in the art. U.S. Pat. No. 4,671,852 issued Jun. 9, 1987 to Beyer et al and assigned to the assignee of the present invention, for example, describes the removal of undesired SiO2 protuberances called "bird's heads" using a combination of chem-mech polishing and Si3N4 blanket deposited at 700 degrees C. by Low Pressure Chemical Vapor Deposition (LPCVD). Among other descriptive material included therein, the patent is useful for its description of the importance of the selection of polishing pads and the dependency of polishing success on the polishing solution chemistry which is set forth in column 6, lines 16-27.
U.S. Pat. No. 4,944,836 issued Jul. 31, 1990 to Beyer et al and assigned to the assignee of the present invention describes a new chem-mech polishing slurry to be used with Si3N4 etch stop layer, the water-based alumina slurry formerly used having been found lacking with respect to the etch rate ratio of AlCu to SiO2.
Not all semiconductor structures are compatible with processing at a high temperature level such as 700 degrees C. For example, in multilevel interconnection levels on wafers with actual circuits, it is necessary to maintain all processing steps at or below about 400 degrees C. in order to prevent diffusion of metal into the underlying devices. Silicon nitride deposited at a temperature compatible with the processing of interconnects, i.e. at about 325 degrees C., has proven to be insufficiently hard to function effectively as an etch stop in such "Back End Of the Line (BEOL)" processes. Aluminum oxide, Al2O3, which is harder than SiO2, has proven to polish at a faster rate than SiO2, presumably due to chemical reactions with the polish, making it an ineffective etch stop material.
Radio frequency (RF) and direct current (DC) sputtering, and hot filament CVD, electron-assisted CVD, thermal CVD and plasma-enhanced CVD (PECVD) of diamond and amorphous hydrogenated diamond-like carbon (DLC) films has been reported. An article by Sawabe et al in Thin Solid Films Vol. 137, pp. 89-99, reports chemical vapor deposition of a carbon film with interplanar spacings in good agreement with reported values for cubic diamond as measured by reflection high energy electron diffraction (RHEED). The authors also report that the film's hardness, thermal conductivity, and electrical resistivity are almost the same as natural diamond. In Japanese Journal of Applied Physics Vol. 25 part 2, no. 6, pp. 519-521, Hirose et al report a film whose measurements of RHEED, Raman spectra, Vicker's hardness, and specific gravity indicate a diamond film.
However, no known art reports that use of a diamond or diamond-like carbon film as a chemical-mechanical polishing etch stop, and no known art reports CVD of such a film at temperatures and having properties compatible with BEOL processing. Hard carbon films are known, but not as an etch stop. Also, compatibility with BEOL processing of such diamond or diamond-like carbon layers is not known in the art.
The chemical-mechanical polish works by chemically dissolving and mechanically abrading the SiO2 layer coating over the metallized wafer. The polish is comprised of an alkali silica slurry. It is important that any etch stop polish slower in the alkaline slurry than the SiO2 or than quartz, a crystalline form of SiO2, or any other material that may be coated over the metallized wafer. Diamond, graphite and amorphous carbon are insoluble in water, acid and alkali and are harder than SiO2 and quartz, DLC layers having a hardness of about 3000 to about 9000 Kg/mm2. The etch stop determines the end point of the polishing process. Diamond and DLC, because of their greater hardness in relation to that of SiO2, make end-point detection in the polishing process controllable. The greater hardness of diamond or DLC in relation to that of SiO2, combined with the chemical inertness of the diamond or DLC means that the etch rate ratio of SiO2:diamond or DLC can equal from about 19:1 up to about 311:1. This ratio range is particularly attractive for feature step heights in BEOL processes. DLC adheres well on most surfaces, such as on Si, SiO2, and carbide forming metals.
Planarization permits improved control of subsequent lithographic steps to prepare for subsequent levels of metallized circuit traces and pads, and to prevent circuit traces from cracking, which can occur when metal traces are disposed over stepped surface features.